OptimalTest has many customer testimonials that show that there is a 1 to 3% yield opportunity to reclaim good devices that are being tested as bad during the testing process. Additionally, Yield Engineers can start to think about using test data combined with Advanced Adaptive Testing techniques to get insights into NPI yield ramps, yield excursions and yield learning like never before.
Optimal Test has patented Advanced Adaptive Testing algorithms for picking and enabling reference dice on wafers. Through the identification of these reference dice and using Advanced Adaptive Testing techniques, Yield Engineers can now afford to augment their test program with additional tests that will give them insight into process parameters used for Yield Learning, which are executed in real-time on the tester. This is a great example of where Advanced Adaptive Test™ is not limited to Test Time Reduction (TTR). It is now possible to use these techniques for Quality Augmentation and Yield Learning purposes as well.
Wafer Map Reconstruction
When die level traceability is available in chips, Yield Engineers can use OT-Portal wafer map reconstruction capabilities on final test data to relate tests that cannot be run at wafer sort back to the actual die location on the original wafer. From there, yield signatures can easily be seen as a large number of devices are tested and mapped back to the wafer map. This capability can also be used to help identify tests that should be inserted at wafer sort to save the significant cost of packaging bad die.
OptimalEnterprise™ allows you to go beyond traditional offline outlier tools. Our Escape Prevention solution encompasses ensuring data integrity and monitoring the health of equipment, processes and operations. Yield Engineers can do a thorough analysis to find parametric excursions that could lead to quality issues while not overkilling yield due to equipment related problems. One of the key benefits is that OptimalTest does all of the integration to Subcon or IDM production floors for Inkless Wafer Mapping based on identified outliers.
Monitoring and Improving Yield
OptimalTest tools will guide your through the process for setting rules that will give you the most in terms of yield while at the same time optimizing tester time. OptimalTest has proven in several customer installations that there is a real opportunity to improve yield by between 1 and 3 percent by quickly identifying defects coming from the testing process. Specific examples include:
- Probe card / load board performance analysis by comparing bin and parametric test data between test sites, allowing you to identify sites that are bad or deteriorating and are impacting device yield
- ATE fleet performance tracking and detection of low performers and outlier testers using statistical rules
- Improved online and offline retest policy to focus on highly recoverable bins: hard bin, soft bin and bin switching data
- Yield improvement via optimized limits
Accurate Yield Calculations
OptimalEnterprise™ and its Semiconductor Information Highway ensure that you will have unprecedented test data integrity. At many major OSAT’s, OptimalTest has already interfaced with workflow systems so Yield Engineers can compare in OT-Portal between device counts reported in the workflow system and device counts gleaned from test data.