The principles of "adaptive testing" have been known for many years, most broadly in the areas of assessment and training for job skills and academics. The advent of computerization allowed traditional testing to be fine-tuned, so that tests could automatically adjust the level of questioning -- easy to difficult -- to challenge a person above or below their ability during the actual test process. In effect, computerized adaptive testing (CAT) tailors the test to the ability of the test taker.

In recent years, the concept of adaptive testing has been applied to the creation and testing of computers, electronics and semiconductors. Papers on the topic have covered it in the realms of software engineering (open operating system standards); VLSI test (current signatures and adaptive test); and semiconductors (parametric electrical wafer probe). (See partial bibliography at end of backgrounder.)

In the 1980s, the first academic papers on adaptive testing appeared. Through subsequent decades, patents and commercial applications about adaptive testing applied to semiconductor testing increasingly appeared, and major companies such as IBM and LSI Logic, as well as universities, became thought leaders in the field.

Notably, in the field of semiconductor testing, adaptive testing figured prominently at the 2004 International Test Conference in North Carolina, framed in the context of yield enhancement as a key test factor.

At ITC 2004, featured speaker Robert Madge, director of advanced product engineering at LSI Logic, addressed traditional design rules and the constrictions they place on optimized yield. He particularly focused on systematic defects affecting yield, an area that is today more significant than two other kinds of defects, random and parametric. Traditional design rules don’t indicate related yield variations and don’t provide sufficient amounts of statistically valid data for insightful decisions for designers. Madge recommended statistical and adaptive testing with adaptive outlier screening as a more effective test strategy for getting yield feedback into the design flow. ort, and extend even to board and system assembly.

Madge’s position reinforced the view of ITC 2004’s keynote speaker, Bernd Koenemann, chief scientist at Mentor Graphics, who addressed the fact that uncaptured design faults, as well as manufacturing process issues, affect chip yields.

The founders of OptimalTest – with extensive experience in software development and semiconductor manufacturing – understood the profound impact that adaptive testing could have on test management. They also understand how the business environment of the semiconductor industry has changed. Today’s semiconductor design, fabrication and test companies (IDMs, foundries, fabless, and assembly test houses) face an end customer who is now predominately in the fast-changing consumer product (rather than more slowly paced IT) arena, so that device designs are more complex and short-lived.

The industry also must contend with fixed costs associated with installed bases of aging automatic test equipment (ATE), end-customer expectations for high quality and reliability, and devices that change so quickly that test equipment quickly becomes obsolete.

Their knowledge about adaptive testing and insight into the semiconductor business environment led OptimalTest’s founders to create their new flagship product, Optimal Test’s Test Management Solutions (OT-TMS). With this product, they take adaptive testing one step further and bring it to the next level: optimal test.

Over the last 25 years it was said of IC testing that "you can test all of the defects part of the time and part of the defects all of the time." OptmalTest has achieved testing of (virtually) all of the defects all of the time.

Optimal testing is not defined by more testing but rather by correct testing. For example, device edges are more fragile than the center of the IC; therefore, more testing might be appropriate regardless of test results. Stressing – a type of test – is currently done the same way for all types of devices; with optimal testing, one might want to stress more along the device edge.

Optimal testing is testing that not only is part of the design feedback loop, but it is part of the design-to-production feedback loop – across the entire test process – and it is customized to each device and each type of device. This new capability has ramifications beyond enhancing yield. It maximizes benefits in the five critical areas – test time reduction, yield, utilization, quality and reliability – that not only affect the quality of the devices themselves but also the financial health and reputation of the semiconductor business operation. Optimal testing can be layered on top of existing testing infrastructures to realize significant improvements in return on investment of installed technical assets as well as lower overall cost of test. Optimal testing goes beyond principles of adaptive testing for what could be a major step in the evolution of test management software solutions and the robustness of the entire semiconductor industry.