If you would like to read additional material about Adaptive Testing, Test Management, Yield Management and other related topics, here are some suggestions:
"In Search of the Optimum Test Set – Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost."
Robert Madge, Brady Benware, Ritesh Turakhia, LSI Corporation; and Robert Daasch, Chris Schuermyer, Jens Ruffler; Portland State University. International Test Conference, International Test Conference (ITC) Proceedings, 2004, pp. 203-212.
"Adaptive Test Adds Value to Parametric Wafer Probe."
B. Bischoff, U. Schiessl, Texas Instruments; and M. Brenner, S. Weinzierl, Keithley Instruments. July, 2004.
"On New Current Signatures and Adaptive Test Technique Combination."
C. Thibeault, Ecole de Technologies Superieure, Montreal Canada. 22nd IEEE VLSI Test Symposium, 2004.
"Creating Value Through Test."
Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Muller. Design, Automation and Test in Europe Conference and Exhibition, 2003.
"Obtaining High Defect Coverage for Frequency- Dependent Defects in Complex ASICs."
Robert Madge, Brady R. Benware, LSI Logic and W. Robert Daasch, Portland State University. IEEE, Sept.-Oct. 2003.
"Screening VDSM Outliers Using Nominal and Sub Threshold Supply Voltage IDDQ."
C. Schuermyer, B. Benware, K. Cota, IC Design and Test Laboratory, Portland State University, Oregon and R. Madge, R. Daasch, L. Ning, LSI Logic. International Test Conference (ITC) Proceedings, 2003.
"Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort."
W. Robert Daasch, K. Cota, James McNames, Portland State University and Robert Madge, LSI Logic Corporation. International Test Conference (ITC) Proceedings, 2002.
"Screening MinVDD Outliers Using Feed-Forward Voltage Testing."
Dr. R. Dassch, IC Design and Test Laboratory, Portland State University, Oregon and R.Madge, B.H Goh, V.S.Rajagopalan, LSI Logic. International Test Conference (ITC) Proceedings, 2002.
"Statistical Post-Processing at Wafer Sort – An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies."
R. Madge, M. Rehani, LSI Logic and W.R. Daasch, K. Cota, IC Design and Test Laboratory, Portland State University, Oregon VLSI Test Symposium (VTS), 2002.
"Neighbor Selection For Variance Reduction in IDDQ and Other Parametric Data."
W.R. Daasch, K. Cota, J. McNames, IC Design and Test Laboratory, Portland State University, Oregon. International Test Conference Proceedings (ITC), 2001.
"Binning for IC Quality: Experimental Studies On the SEMATECH Data."
D. Singh, D.R. Lakin, II, P. Nigh, Dept. of Electrical Eng., Auburn University, Alabama. Defect and Fault Tolerance in VLSI Systems, IEEE International Symposium, 1998.